The present invention relates generally to electronic circuit packages and methods of fabrication therefor, and more particularly, to integrated circuit packages having bond pads that are directly connected with vertically-oriented conductive layers, rather than with vias or horizontally-oriented conductive layers.
Signals, power, and ground typically are routed to and from an integrated circuit (IC) through conductive bond pads on the bottom of the IC, which mate with complementary bond pads on the top surface of an IC package. This is common for ICs that use ball grid array (BGA) (e.g., xe2x80x9cflip chipsxe2x80x9d) and land grid array (LGA) interconnection technologies. Alternatively, wire bonds are often used to electrically connect an IC and an IC package.
FIG. 1 illustrates a cross-sectional view of an electronic assembly that includes an IC 102 and package 104 in accordance with the prior art. Bond pads 106 on the bottom surface of IC 102 electrically connected to complementary bond pads 108 on the top surface of IC package 104 using solder bumps or balls 110. The IC package bond pads 108 are, in turn, electrically connected to vias 112. Vias 112 are plated and/or filled holes in the package""s dielectric layers, which are used to interconnect various conductive layers 114 within the package 104, and/or connectors 108, 116 on the top and/or bottom surfaces, respectively, of the package 104.
Package 104 is electrically connected to a socket 118 or interposer (not shown), through soldered or pinned connectors 116. Socket 118, in turn, is electrically connected to a printed circuit (PC) board 122 using pinned or soldered connections. Alternatively, package 104 can be connected directly to PC board 122 without the use of an intermediate socket or interposer. Using prior art technologies, input/output (I/O) signals, power, and ground are supplied from PC board 122 to IC 102 through socket 118, connectors 116, conductive layers 114, vias 112, pads 108, and solder balls 110.
FIG. 2 illustrates a top view of an IC package, which includes multiple rows of pads 202, 204 in accordance with the prior art. Pads 204 within a center region 206 of the package typically are allocated to power and ground. In contrast, pads 202 within a peripheral region 208 typically are allocated to I/O signals.
Current packaging technologies are limited in the location and number of pads 202 that can be dedicated to 1/0 signals because of the need to separately fan out, through vias and traces, each I/O signal from the IC pad pitch to the package pad pitch. In current flip chip packages, only the outer few rows of pads 202 can be dedicated to I/O signals. Thus, for example, in a package having 40xc3x9740 rows of pads, only about 300 pads can be dedicated to I/O signals, while about 1300 pads can be dedicated to power and ground. In order to increase the number of I/O signals that can be fanned out, it is necessary to use finer design rules (e.g., smaller line spacing and pad pitches), increase the size of the IC, and/or increase the number of package layers. Using finer design rules translates to more expensive materials and manufacturing techniques.
IC package size and package layer increases are undesirable in many applications, because the consumer-driven trend within industry is to reduce the size of electronic systems. Accordingly, what are needed are package designs that enable higher I/O counts without increases in IC sizes, package layer counts or finer package design rules.
In addition to issues relating to limited numbers of I/O signals, noise in the power and ground lines increasingly becomes a problem with current IC package designs. This is primarily due to escalating circuit frequencies, which result in increased high frequency transients. To reduce such noise, capacitors known as decoupling capacitors are often used to provide a stable signal or stable supply of power to the circuitry. Decoupling capacitors are also used to suppress unwanted radiation, to dampen voltage overshoot when an electronic device (e.g., a processor) is powered down, and to dampen voltage droop when the device powers up.
Decoupling capacitors are generally placed as close as practical to a die load in order to increase the capacitors"" effectiveness. Often, the capacitors are surface mounted to the die side or land side of the package upon which the die is mounted, or embedded within the package itself. Referring again to FIG. 1, die side capacitors 130 (xe2x80x9cDSCxe2x80x9d) and land side capacitors (not shown) (xe2x80x9cLSCxe2x80x9d) are mounted on IC package 104 in accordance with the prior art. DSCs 130, as their name implies, are mounted on the same side of the package 102 as the IC 102. In contrast, LSCs are mounted on the opposite side of the package 104 as the IC 102. Embedded chip capacitors (not shown) (xe2x80x9cECCxe2x80x9d) can be embedded within the package 104 and electrically connected to package planes and/or pads through conductive vias.
When a xe2x80x9cfirst levelxe2x80x9d voltage droop occurs, the electrically closest, off-chip capacitors (e.g., ECCs, if they are available) will respond first to supply the current needed to bolster the die voltage. When the charge stored within these first level capacitors begins to deplete, a xe2x80x9csecond levelxe2x80x9d voltage droop occurs, and other off-chip capacitors (e.g., DSCs and/or LSCs) will respond, if they are available.
The capacitors"" terminals are connected to the integrated circuit load through conductive structures (e.g., pads, vias, and power or ground planes), thus enabling the capacitors 130 to provide decoupling capacitance to the integrated circuit. Connection of the capacitors 130 to the load and to each other through the package""s conductive structures results in xe2x80x9cverticalxe2x80x9d and xe2x80x9clateralxe2x80x9d inductances to exist in the supply and return loop between the capacitors 130 and the IC load. These vertical and lateral inductances tend to slow the response time of off-chip capacitors, which may cause the first and second level voltage droops to be unacceptably low.
Vertical inductance issues can be addressed by placing off-chip capacitors 130 as electrically close as possible to the die load, such as by using ECCs, which typically can be placed closer to the load than surface mounted capacitors. Similarly, lateral inductance issues can be addressed by placing adjacent capacitors as close as possible to each other.
As the frequencies and edge rates of electronic devices continue to advance, there is an increasing need for higher levels of decoupling capacitance. However, increasing the numbers of discrete decoupling capacitors typically results in increased package sizes. Therefore, what are needed are packages that can provide higher levels of decoupling capacitance, without increased package sizes, and at reduced inductance levels.